As semiconductor devices have become highly integrated, patterns therein have been formed with greatly reduced widths and intervals therebetween. Accordingly, precise technologies for forming finer patterns in semiconductor devices are increasingly being demanded. A width of a gate in a semiconductor device having a high integration degree may decrease according to a decrease of a design rule in the semiconductor device. Hence, in order to ensure a minute width and an increased channel length, methods of manufacturing semiconductor devices including a recessed gate electrode have been developed.
A conventional recessed gate electrode is disclosed in Korean Patent No. 304,717, Japanese Laid-Open Patent Publication No. 2000-349289 and U.S. Pat. No. 6,762,098 issued to Hshieh et al. Particularly, Korean Patent No. 236048 describes a transistor including a recessed gate electrode having an enlarged lower portion.
FIGS. 1A to 1F are cross-sectional views illustrating a method of manufacturing a transistor having a recessed gate electrode in accordance with Korean Patent No. 236048.
Referring to FIG. 1A, a first photosensitive film is formed on a substrate 1 having an active region and a field region defined by an isolation layer 3, and then the first photosensitive film is exposed and developed to form a first photosensitive film pattern 6 partially exposing the active region of the substrate 1.
Using the first photosensitive film pattern 6 as an ion implantation mask, impurities are doped into an exposed portion of the active region, thereby forming a first impurity region 9 and a channel region 12. The channel region 12 is formed on the first impurity region 9.
Referring to FIG. 1B, after removing the first photosensitive film pattern 6, a second photosensitive film pattern 14 is formed on the substrate 1 to expose the channel region 12.
The exposed channel region 12 is partially etched using the second photosensitive film pattern 14 as an etching mask so that a first trench 15 and a second trench 16 are formed on the channel region 12.
Referring to FIG. 1C, a first oxide layer is formed on the active region and on bottoms and sidewalls of the first and the second trenches 15 and 16 after removing the second photosensitive film pattern 14.
Portions of the first oxide layer on the active region and the bottoms of the first and the second trenches 15 and 16 are removed to thereby form first oxide layer patterns 18 on the sidewalls of the first and the second trenches 15 and 16.
Referring to FIG. 1D, a third photosensitive film pattern 21 is formed on the substrate 1 to expose the bottoms of the first and the second trenches 15 and 16 and also to expose the first oxide layer patterns 18.
Portions of the channel region 12 exposed by the first and the second trenches 15 and 16 are partially etched using the third photosensitive film pattern 21 and the first oxide layer patterns 18 as etching masks. Thus, lower portions of the first and the second trenches 15 and 16 are enlarged in rounded shapes. The first impurity region 9 is exposed by the first and the second trenches 15 and 16 having the enlarged lower portions.
Referring to FIG. 1E, the third photosensitive film pattern 21 and the first oxide layer patterns 18 are sequentially removed, and then second oxide layer patterns 24 are formed on sidewalls of the enlarged lower portions of the first and the second trenches 15 and 16.
A fourth photosensitive film pattern (not shown) is formed on the substrate 1 to cover the first trench 15. The fourth photosensitive film pattern exposes the bottom of the second trench 16. A portion of the second oxide layer patterns 24 on the bottom of the second trench 16 is removed using the fourth photosensitive film pattern as an etching mask. Hence, a portion of the first impurity region 9 is exposed through the second trench 16.
Referring to FIG. 1F, after removing the fourth photosensitive film pattern, a polysilicon layer is formed on the substrate 1 to fill up the first and the second trenches 15 and 16.
A portion of the polysilicon layer on the active region is removed by an etch-back process to thereby fort recessed gates 27 having enlarged lower portions buried in the first and the second trenches 15 and 16.
After a fifth photosensitive film pattern (not shown) is formed on the substrate 1 to expose the recessed gates 27, second impurity regions 30 are formed at upper portions of the recessed gates 27 by implanting impurities using the fifth photosensitive film pattern as a mask.
As for the above-mentioned method for manufacturing a transistor having the recessed gate, a void or a seam is generated in the enlarged lower portion of the recessed gate so that electrical characteristics of the transistor may deteriorate. This problem will be described in detail with reference to the accompanying drawings.
FIGS. 2A and 2B are electron microscopic pictures showing cross-sections of a conventional transistor having a recessed gate.
Referring to FIG. 2A, a polysilicon layer filling a trench having an enlarged lower portion is formed so as to form the recessed gate. An upper portion of the trench has a reduced width, for example, about 60 nm when a design rule of the transistor decreases. Thus, a void or a seam occurs in a lower portion of the polysilicon layer filling the trench, which has the enlarged lower portion. That is, the void or the seam is generated in a lower portion of the recessed gate.
As shown in FIG. 2B, the void or the seam generated in the lower portion of the recessed gate moves toward the gate insulation layer enclosing the recessed gate during subsequent processes for forming the transistor. Since a channel region of the transistor is formed around the lower portion of the recessed gate, the transistor may have poor electrical characteristics when the void or the seam makes contact with the channel region. In other words, when voids or seams are in contact with channel regions, threshold voltages of transistors in a unit cell of a semiconductor device may be considerably irregular and also leakage currents may be greatly increased through portions of the channel regions making contact with the voids or the seams. As a result, the transistor may have poor electrical characteristics when the void or the seam is in contact with the channel region thereof.